library verilog;
use verilog.vl_types.all;
entity tc_si_to_mt is
    generic(
        t0_addr_w       : integer := 3;
        t0_addr         : integer := 0;
        t17_addr_w      : integer := 3;
        t1_addr         : integer := 1;
        t2_addr         : integer := 2;
        t3_addr         : integer := 3;
        t4_addr         : integer := 4;
        t5_addr         : integer := 5;
        t6_addr         : integer := 6;
        t7_addr         : integer := 7
    );
    port(
        i0_wb_cyc_i     : in     vl_logic;
        i0_wb_stb_i     : in     vl_logic;
        i0_wb_cab_i     : in     vl_logic;
        i0_wb_adr_i     : in     vl_logic_vector(31 downto 0);
        i0_wb_sel_i     : in     vl_logic_vector(3 downto 0);
        i0_wb_we_i      : in     vl_logic;
        i0_wb_dat_i     : in     vl_logic_vector(31 downto 0);
        i0_wb_dat_o     : out    vl_logic_vector(31 downto 0);
        i0_wb_ack_o     : out    vl_logic;
        i0_wb_err_o     : out    vl_logic;
        t0_wb_cyc_o     : out    vl_logic;
        t0_wb_stb_o     : out    vl_logic;
        t0_wb_cab_o     : out    vl_logic;
        t0_wb_adr_o     : out    vl_logic_vector(31 downto 0);
        t0_wb_sel_o     : out    vl_logic_vector(3 downto 0);
        t0_wb_we_o      : out    vl_logic;
        t0_wb_dat_o     : out    vl_logic_vector(31 downto 0);
        t0_wb_dat_i     : in     vl_logic_vector(31 downto 0);
        t0_wb_ack_i     : in     vl_logic;
        t0_wb_err_i     : in     vl_logic;
        t1_wb_cyc_o     : out    vl_logic;
        t1_wb_stb_o     : out    vl_logic;
        t1_wb_cab_o     : out    vl_logic;
        t1_wb_adr_o     : out    vl_logic_vector(31 downto 0);
        t1_wb_sel_o     : out    vl_logic_vector(3 downto 0);
        t1_wb_we_o      : out    vl_logic;
        t1_wb_dat_o     : out    vl_logic_vector(31 downto 0);
        t1_wb_dat_i     : in     vl_logic_vector(31 downto 0);
        t1_wb_ack_i     : in     vl_logic;
        t1_wb_err_i     : in     vl_logic;
        t2_wb_cyc_o     : out    vl_logic;
        t2_wb_stb_o     : out    vl_logic;
        t2_wb_cab_o     : out    vl_logic;
        t2_wb_adr_o     : out    vl_logic_vector(31 downto 0);
        t2_wb_sel_o     : out    vl_logic_vector(3 downto 0);
        t2_wb_we_o      : out    vl_logic;
        t2_wb_dat_o     : out    vl_logic_vector(31 downto 0);
        t2_wb_dat_i     : in     vl_logic_vector(31 downto 0);
        t2_wb_ack_i     : in     vl_logic;
        t2_wb_err_i     : in     vl_logic;
        t3_wb_cyc_o     : out    vl_logic;
        t3_wb_stb_o     : out    vl_logic;
        t3_wb_cab_o     : out    vl_logic;
        t3_wb_adr_o     : out    vl_logic_vector(31 downto 0);
        t3_wb_sel_o     : out    vl_logic_vector(3 downto 0);
        t3_wb_we_o      : out    vl_logic;
        t3_wb_dat_o     : out    vl_logic_vector(31 downto 0);
        t3_wb_dat_i     : in     vl_logic_vector(31 downto 0);
        t3_wb_ack_i     : in     vl_logic;
        t3_wb_err_i     : in     vl_logic;
        t4_wb_cyc_o     : out    vl_logic;
        t4_wb_stb_o     : out    vl_logic;
        t4_wb_cab_o     : out    vl_logic;
        t4_wb_adr_o     : out    vl_logic_vector(31 downto 0);
        t4_wb_sel_o     : out    vl_logic_vector(3 downto 0);
        t4_wb_we_o      : out    vl_logic;
        t4_wb_dat_o     : out    vl_logic_vector(31 downto 0);
        t4_wb_dat_i     : in     vl_logic_vector(31 downto 0);
        t4_wb_ack_i     : in     vl_logic;
        t4_wb_err_i     : in     vl_logic;
        t5_wb_cyc_o     : out    vl_logic;
        t5_wb_stb_o     : out    vl_logic;
        t5_wb_cab_o     : out    vl_logic;
        t5_wb_adr_o     : out    vl_logic_vector(31 downto 0);
        t5_wb_sel_o     : out    vl_logic_vector(3 downto 0);
        t5_wb_we_o      : out    vl_logic;
        t5_wb_dat_o     : out    vl_logic_vector(31 downto 0);
        t5_wb_dat_i     : in     vl_logic_vector(31 downto 0);
        t5_wb_ack_i     : in     vl_logic;
        t5_wb_err_i     : in     vl_logic;
        t6_wb_cyc_o     : out    vl_logic;
        t6_wb_stb_o     : out    vl_logic;
        t6_wb_cab_o     : out    vl_logic;
        t6_wb_adr_o     : out    vl_logic_vector(31 downto 0);
        t6_wb_sel_o     : out    vl_logic_vector(3 downto 0);
        t6_wb_we_o      : out    vl_logic;
        t6_wb_dat_o     : out    vl_logic_vector(31 downto 0);
        t6_wb_dat_i     : in     vl_logic_vector(31 downto 0);
        t6_wb_ack_i     : in     vl_logic;
        t6_wb_err_i     : in     vl_logic;
        t7_wb_cyc_o     : out    vl_logic;
        t7_wb_stb_o     : out    vl_logic;
        t7_wb_cab_o     : out    vl_logic;
        t7_wb_adr_o     : out    vl_logic_vector(31 downto 0);
        t7_wb_sel_o     : out    vl_logic_vector(3 downto 0);
        t7_wb_we_o      : out    vl_logic;
        t7_wb_dat_o     : out    vl_logic_vector(31 downto 0);
        t7_wb_dat_i     : in     vl_logic_vector(31 downto 0);
        t7_wb_ack_i     : in     vl_logic;
        t7_wb_err_i     : in     vl_logic
    );
end tc_si_to_mt;
